Reading RX FIFO Latency

The datapath latency through the RX FIFO is calculated statistically using RXLATCLK, which is asynchronous to XCLK. RX_SAMPLE_COUNT in CH*_RX_PCS_CFG1 determines the number of RXLATCLK cycles over which averaging takes place. RXLATCLK needs to be asynchronous in both phase and frequency to both the write clock and the read clock. The RXLATCLK has the same range as the RXUSRCLK, greater than zero frequency and less than the max USRCLK frequency. The measured latency value in RX_FIFO_LATENCY is updated once per sampling period, and located in COE_STATUS_RX_GB_DBG6 for the 160x512 FIFO and COE_STATUS_RX_GB_DBG8 for the 160x320 FIFO.

These settings are used to read the latency:

• Set CH*_RX_PCS_CFG1[24:22] (RX_SAMPLE_COUNT)
  • A higher averaging period gives a more accurate latency value.
• For the 160x512 FIFO, read CH*_COE_STATUS_RX_GB_DBG6[16:0] (RX_FIFO_LATENCY): The value is in units of 1/8 UI.
• For the 160x320 FIFO, read CH*_COE_STATUS_RX_GB_DBG8[16:0] (RX_FIFO_LATENCY): The value is in units of 1/8 UI.
• The actual latency is RX_FIFO_LATENCY plus a fixed value.