Versal ACAP GTM Transceivers Architecture Manual (AM017)

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1.0 English

The RX clock data recovery (CDR) circuit in each Versal ACAP GTM transceiver channel extracts the recovered clock and data from an incoming data stream. The following figure illustrates the architecture of the CDR block. Clock paths are shown with dotted lines for clarity.

Figure 1. CDR Block Diagram

The GTM transceiver employs the baud-rate phase detection CDR architecture. Incoming data first goes through receiver equalization and ADC where the data is sampled. The sampled data then moves through FFE and DFE before feeding to the CDR state machine and downstream transceiver blocks.

The LCPLL provides a base clock to the phase interpolator. The phase interpolator in turn produces fine, evenly spaced sampling phases to allow the CDR state machine to have fine phase control. The CDR state machine can track incoming data streams that can have a frequency offset from the local PLL reference clock.