Reading TX FIFO Latency

Versal ACAP GTM Transceivers Architecture Manual (AM017)

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The datapath latency through the TX FIFO is calculated statistically using TXLATCLK, which is asynchronous to XCLK. TX_SAMPLE_PERIOD in CH*_TX_PCS_CFG1 determines the number of TXLATCLK cycles over which averaging takes place. The measured latency value in TX_FIFO_LATENCY is updated once per sampling period, and located in COE_STATUS_TX_GB_DBG6 for the 512x128 FIFO and COE_STATUS_TX_GB_DBG8 for the 320x128 FIFO.

These settings are used to read the latency:

    • A higher averaging period gives a more accurate latency value.
  • For the 512x128 FIFO, read CH*_COE_STATUS_TX_GB_DBG6[17:0] (TX_FIFO_LATENCY): The value is in units of 1/8 UI.
  • For the 320x128 FIFO, read CH*_COE_STATUS_TX_GB_DBG8[17:0] (TX_FIFO_LATENCY): The value is in units of 1/8 UI.
  • The actual latency is TX_FIFO_LATENCY plus a fixed value.