Ports and Attributes

Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017)

Document ID
AM017
Release Date
2024-09-05
Revision
1.1 English

The following table shows the RX interface ports.

Table 1. RX Interface Ports
Port Direction Clock Domain Description
CH[0/1/2/3]_RXDATA[255:0] Output RXUSRCLK The bus for receiving data.
CH[0/1/2/3]_RXUSRCLK Input CLOCK This port is used to provide a clock for the internal RX PCS datapath.

The following table shows the RX interface attributes.

Table 2. RX Interface Attributes
RX Interface Attributes
Attribute Address
CH0_RX_PCS_CFG0 0x0C14
CH1_RX_PCS_CFG0 0x0D14
CH2_RX_PCS_CFG0 0x0E14
CH3_RX_PCS_CFG0 0x0F14
Label Bit Field Description
RX_USRCLK_SEL [15:14]

Clock selection for data usage at fabric interface.

2'b00: USRCLK for single channel data fabric interface usage (full density)

2'b01: Adjacent channel user clock for dual channel data fabric interface usage (half density)

2'b10: Reserved.

2'b11 Reserved.

RX_PMA_DATA_WIDTH [4:4]

Controls the width of the RX internal PCS datapath.

0: 80-bit internal datapath width (NRZ)

1: 160-bit internal datapath width (PAM4)

RX_DATA_WIDTH [3:0]

Controls the RX interface width.

4'b0100: 32-bit

4'b0101: 40-bit

4'b0110: 64-bit

4'b0111: 80-bit

4'b1000: 128-bit

4'b1001: 160-bit

4'b1010: 256-bit

4'b1011: 320-bit

4'b1100: 512-bit