Depending on the TXUSRCLK frequency, there are different ways in which the Versal architecture clock resources can be used to drive the parallel clock for the TX interface. The following figure shows TXOUTCLK being used to drive TXUSRCLK in varying data widths.
- Depending on the input reference clock frequency and the required line rate, a BUFG_GT with the appropriate TXOUTCLKCTL setting is required. The Versal adaptive SoC Transceivers Wizard creates a sample design based on different design requirements for most cases.
- When TXOUTCLK from one lane is used to drive multiple lanes (TXUSRCLK), the corresponding PLL for each lane must share the same reference clock.
Figure 1. TXOUTCLK Drives TXUSRCLK
