Versal ACAP GTM Transceivers Architecture Manual (AM017)

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The Versal architecture GTM transceiver provides the highest performances and integration at 7 nm, including serial I/O bandwidth and logic capacity. As the industry's high-end FPGA at the 7 nm process node, this family is ideal for applications including 400G networking, large-scale ASIC prototyping, and emulation.

The GTM transceiver in the Versal architecture is a power-efficient transceiver, supporting line rates between 9.5 Gb/s and 112 Gb/s. Based on the available PLL divider configurations in the GTM transceivers, the following line rates are supported:

  • NRZ Modulation:
    • 9.5 Gb/s – 15 Gb/s
    • 19 Gb/s – 29 Gb/s
  • PAM4 Modulation
    • 19 Gb/s – 30 Gb/s
    • 38 Gb/s – 60 Gb/s
    • 76 Gb/s – 112 Gb/s

The Versal ACAP GTM transceiver is Xilinx's highest performance PAM4 enabled transceiver and is highly configurable and tightly integrated with the programmable logic resources of the FPGA. The following table summarizes the features by functional group that support a wide variety of applications.

Table 1. GTM Transceiver Features
Group Feature
PCS PRBS generator and checker
Programmable FPGA logic interface
PMA LC tank oscillator PLL (LCPLL) for best jitter performance
Flexible clocking with two LCPLLs per Quad 1 (four channels)
Programmable transmitter (TX) output
TX FIR filter with de-emphasis controls
Continuous time linear equalization (CTLE)
Decision feedback equalization (DFE)
Feed forward equalization (FFE)
  1. A Quad is a cluster or set of four GTM transceiver channels, one GTME5_QUAD primitive, two differential reference clock pin pairs, and analog supply pins. There is no channel primitive.
  2. A GTM Quad can function in full density or half density mode. In full density mode, all four channels in the Quad are functional. In half density mode, only two channels in the quad are functional: channel 0 or 1, and channel 2 or 3.
  3. Full density mode is supported for all NRZ line rates.
  4. Full density mode is supported for line rates up to 58 Gb/s PAM4. Line rates greater than 58 Gb/s PAM4 must use half density mode.
  5. Half density mode must be used by designs using fabric interface data widths of 320 and 512 bits. For more information, see TX Interface and RX Interface.

The GTM transceiver supports NRZ and PAM4 modulation as well as the following protocols:

  • 400GE CDAUI4
  • 400GE CDAUI8
  • 100GE CAUI2
  • 100GE CAUI4
  • 100GE CAUI1
  • 50GE LAUI
  • 50GE LAUI2
  • Multirate CPRI from 10.1 Gb/s to 100 Gb/s
  • Interlaken at 51.5625 Gb/s, 25 Gb/s, 12.5 Gb/s
  • OTU4
  • 112G XSR
  • 56 Gb/s PAM4 Backplane
  • 56.52 Gb/s PAM4 Midplanes
  • 28.21 Gb/s PAM4 Backplanes
  • 10GBASE-KR
  • 802.3bj Backplanes and Cables

The first-time user is recommended to read High-Speed Serial I/O made Simple, which discuss high-speed serial transceiver technology and its applications. The Vivado® IP integrator or the transceiver Wizard design flow is recommended to automatically configure the GTM transceiver to support configurations for different protocols or perform custom configurations. The GTM transceiver offers a data rate range and features that allow physical layer support for various protocols.

The following figure illustrates the clustering of four transceiver channels and two high speed clocking (HSCLK) blocks to form the GTME5_QUAD primitive.

Figure 1. GTM Quad Configuration

Four channel clustered together with two HSCLK blocks form a Quad or Q. Each HSCLK block contain one LC-tank PLL (LCPLL). The LCPLL from each HSCLK can provide clock to any of the four channels inside the same Quad. Each channel consists of a transmitter and a receiver. The following figure illustrates the topology of the GTM channel.

Important: Half density mode must be used for line rates greater than 58 Gb/s (PAM4), and for fabric interface data widths of 320 and 512 bits. For more information, see TX Interface and RX Interface.
Figure 2. GTM Channel Topology