The fabric configuration interface (APB3) allows the user to dynamically update the attributes of the GTME5_QUAD primitive. The APB3 interface is a processor-friendly synchronous interface with an address bus (APB3PADDR) and separate data buses for reading (APB3PRDATA) and writing (APB3PWDATA) configuration data to the primitive. An enable signal (APB3PENABLE), a read/write signal (APB3PWRITE), and a ready/valid signal (APB3PREADY) are the control signals that implement read and write operations, indicate operation completion, and indicate the availability of data. When TXOUTCLK from one lane is used to drive multiple lanes (TXUSRCLK), the corresponding PLL for each lane must share the same reference clock.