Serial Clock Divider

Versal ACAP GTM Transceivers Architecture Manual (AM017)

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Each transmitter PMA module has a D divider that divides down the clock from the PLL for lower line rate support. This serial clock divider D can be set statically for applications with a fixed line rate or changed dynamically for protocols with multiple line rates.

To use the divider D in fixed line rate applications, RXOUT_DIV must be set to the appropriate value, and the CH*_RXRATE port should be tied to 8'b00000000.

For multiple line rate applications, the CH*_TXRATE port is used to dynamically select the line rate settings, which include the appropriate divider values. See Rate Change for more details.