Versal ACAP GTM Transceivers Architecture Manual (AM017)

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In the transceiver TX datapath, the TX FIFO acts as a buffer between the two clock domains: the fabric (TXUSRCLK), and the PMA parallel clock (XCLK). To transmit data, the TX FIFO provides data width conversion between these clock domains when necessary, depending on the operating data width and encoding mode. The following figure shows the TX datapath clock domains.

Figure 1. Transmitter Datapath Clock Domains

The GTM transmitter includes a TX FIFO to support data width conversion when data crosses from TXUSRCLK to XCLK domain. The buffer does not tolerate ppm differences, and only provides phase compensation between the two clocks. The TX FIFO inside the GTM transceiver must always be used and cannot be bypassed.