SelectIO Pin Definitions

Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013)

Document ID
Release Date
1.4 English
Table 1. SelectIO Pin Definitions.
Pin Name Direction Description
IO Bidirectional

XPIO pin names consist of:

  • L[1 to 24][P or N]: Differential pair number with P (positive) and N (negative)
  • N[0 to 8]P[0 to 5]: XPHY nibble number and pin number within the nibble (NIBBLESLICE number)
  • M[0 to number of triplets]P[0 to 161]: Triplet number and pin within the triplet
  • [bank number]: Bank number

The XP IOB block provides resources to enable high-speed interfaces between the programmable logic (PL) and the system outside the device. The XP IOB resources are designed to accommodate the signaling needs for high-speed memory and chip-to-chip interfaces that are powered between 1.0V and 1.5V. The XP IOB provides internal termination, internal reference generation, support for a diverse set of I/O standards, driver emphasis, and receiver equalization. These features allow the XP IOB to integrate with a diverse range of systems.

High-density (HD) I/O banks are resources designed to support I/O standards with voltages ranging from 1.8V to 3.3V. HD I/Os support single ended and pseudo-differential I/O bidirectional signaling operating at data rates of up to 400 Mb/s. Limited support for true differential inputs (with external termination) is also available to support LVDS and LVPECL clock inputs. HD I/O banks contain interface logic (HD IOL) that includes registers, a DPLL, and static delay lines to support asynchronous, system synchronous, and clock-based source synchronous interfaces.

GC/HDGC Bidirectional Global clock (GC) inputs provide dedicated, high-speed access to the internal global and regional clock resources. GC inputs use dedicated routing and must be used for clock inputs where the timing of various clocking features is imperative. General-purpose I/O with local interconnects must not be used for clock signals.
IO_VR N/A This pin is for the DCI voltage reference resistor, one per bank row: IO_VR_700 and IO_VR_800. Tie to VCCO_700 and VCCO_800, respectively, with a reference resistor.
C4CCIO_PAD Input Reference clock inputs for high-bandwidth memory banks. Each clock pair serves as the external reference clock for each HBM stack PAD0_0/PAD1_0 for stack 0 and PAD0_1/PAD1_1 for stack 1. PAD0 is the P-side and PAD1 is the N-side for each C4CCIO_PAD pair.