Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013)

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Table 1. PMCMIO, LPDMIO, PMCDIO Pin Definitions
Pin Name Direction Description
PMC_MIO[0 to 51] Bidirectional Platform management controller (PMC) multiplexed I/O (MIO)
LPD_MIO[0 to 25] Bidirectional Low-power domain (LPD) MIO
MODE[0 to 3] 1 Input The MODE selection pins are used to select the boot mode of the device. The value of these pins is captured on the rising edge of POR_B.
ERROR_OUT Output The ERROR_OUT pin is open drain with a weak internal pull-up. An external pull-up is recommended. ERROR_OUT is 3-stated and pulled High when an error occurs in the device.
RTC_PADO Output Real-time clock (RTC) crystal output
RTC_PADI Input RTC crystal input
PUDC_B 1 Input The pull-up during configuration (PUDC_B) pin is used to select the behavior of the XPIO or HDIO during configuration. If the PUDC_B pin is High, then the XPIO and HDIO are put into tristate mode. If the PUDC_B is Low, then internal pull-ups at each XPIO and HDIO are enabled. The PUDC_B pin does not affect the PS or PMC I/O during boot and configuration.
DONE Bidirectional The DONE pin is open drain with a weak internal pull-up resistor. An external pull-up is recommended. DONE is 3-stated and pulled High when the boot sequence is complete.
REF_CLK 1 Input/Output The reference clock is required for all boot modes. The REF_CLK is also the input clock to the PMC PLL and is required for the slave boot interface software register access.
POR_B 1 Input

Active-Low POR_B pin is the global power-on reset for the Versal Prime, Versal AI Core, Versal Premium, Versal HBM and Versal AI Edge devices.

During the PMC domain power-on sequence, the POR_B input must be asserted Low and continue to be asserted for a minimum duration of TPOR_B (10 µs) after all the required supplies of the PMC power domain (VCCO_500, VCCO_501, and VCCO_503, VCC_PMC, VCCAUX_PMC, and VCCAUX_SMON) have reached minimum operating voltage levels. If other power domains are powered with the PMC domain and are expected to be functional at initial power-on without additional power management, then the POR_B input must be held Low until all applicable power domain supplies have reached minimum voltage levels. After PMC domain power-on, POR_B must be deasserted High to complete the device power-on-reset (pro). The recommended power-down sequence is the reverse of the power-on sequence with POR_B held Low during power-down of the PMC power domain.​

For more information consult the Power Design Manager (PDM) tool (download at

TCK Input JTAG test clock
TDI Input JTAG test data input
TDO Output JTAG test data output
TMS Input JTAG test mode select
  1. Some devices include multiple instances of these pins. Refer to the PMC Dedicated Pins section of Versal Adaptive SoC PCB Design User Guide (UG863) for connection guidelines.