BSDL Device Model Files

Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013)

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1.4 English

A boundary-scan description language (BSDL) file is a model of the JTAG instructions and JTAG registers for a device. The file includes a map between the JTAG boundary register and package pinout, as defined by the IEEE Std 1149.1. JTAG board test tools use the BSDL device model file for generating tests for device-package pins that check board-level interconnects/traces. BSDL files are provided for each production and engineering sample package file.

Versal platform BSDL device model files are available in the device models area of the support downloads webpage at: