XPIO-PL Interface Techniques for Timing - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

Boundary logic interface flip-flops exist in hardware between the XPIO-programmable logic (PL) interface, which you can use to improve timing. Dedicated blocks in the XPIO such as the XPHY Logic, I/O Logic, and clock-modifying blocks have boundary logic interface flip-flops. You can apply boundary logic interface (BLI) constraints to flip-flops in your design to automatically take advantage of this hardware feature during design placement. In this example, the data paths to and from the I/O Logic cells ODDRE1 and IDDRE1 in the XPIO are taking advantage of the BLI FFs.

set_property BLI TRUE [get_cells {oddr_D1_BLI_reg oddr_D2_BLI_reg}]
set_property BLI TRUE [get_cells {iddr_Q1_BLI_reg iddr_Q2_BLI_reg}]]

The following figure shows the resulting placement and connectivity from setting the BLI property to TRUE.

Figure 1. Placement of XPIO-PL Interface BLI Flip-Flops for ODDRE1 and IDDRE1