Check Inferred Logic - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-11-19
Version
2021.2 English

As you code your design, be aware of the logic being inferred. Monitor the following conditions for additional pipelining considerations:

  • Cones of logic with large fanin

    For example, code that requires large buses or several combinational signals to compute an output.

  • Blocks with restricted placement or slow clock-to-out or large setup requirements

    For example, block RAMs without output registers or arithmetic code that is not appropriately pipelined.

  • Forced placement that causes long routes

    For example, a pinout that forces a route across the chip might require pipelining to allow for high-speed operation.

  • Logic comprised of large XOR functions

    Large XOR functions often have high switch rates that can generate large dynamic power dissipation. Pipelining these functions can reduce switching, which positively impacts power consumption of the described circuit.

In the following figure the clock speed is limited by:

  • Clock-to out-time of the source flip-flop
  • Logic delay through four levels of logic
  • Routing associated with the four function generators
  • Setup time of the destination register
Figure 1. Before Pipelining Diagram
Page-1 Sheet.1 D Flip-Flop.17 Sheet.3 D D Sheet.4 Q Q Sheet.5 LUT LUT Standard Arrow.7 Standard Arrow.8 Standard Arrow.9 Standard Arrow.11 Sheet.10 LUT LUT Standard Arrow.12 Standard Arrow.15 Standard Arrow.14 Sheet.14 LUT LUT Arrow Standard Right.19 Standard Arrow.17 Standard Arrow.18 Sheet.18 LUT LUT Arrow Standard Right.24 Standard Arrow.25 Standard Arrow.26 Sheet.22 D Flip-Flop.28 Sheet.24 D D Sheet.25 Q Q Standard Arrow.28 Standard Arrow.29 Standard Arrow.13 Arrow Standard Right.18 Arrow Standard Right.23 Arrow Standard Right.33 Sheet.32 Slow_Clock Slow_Clock Sheet.39 reg0 reg0 Sheet.41 reg1 reg1 Sheet.44 x-number text box X13429-042122 X13429-042122

The following figure is an example of the same data path shown in the Before Pipelining diagram. Because the flip-flop is contained in the same slice as the function generator, the clock speed is limited by the clock-to-out time of the source flip-flop, the logic delay through one level of logic, one routing delay, and the setup time of the destination register. In this example, the system clock runs faster after pipelining than before pipelining.

Figure 2. After Pipelining Diagram
Page-1 Sheet.1 D Flip-Flop.17 Sheet.3 D D Sheet.4 Q Q Sheet.5 LUT LUT Standard Arrow.7 Standard Arrow.9 Standard Arrow.10 Standard Arrow.11 Sheet.10 LUT LUT Standard Arrow.14 Standard Arrow.15 Standard Arrow.16 Sheet.14 LUT LUT Arrow Standard Right.19 Standard Arrow.20 Standard Arrow.21 Sheet.18 LUT LUT Arrow Standard Right.24 Standard Arrow.25 Standard Arrow.26 Sheet.22 D Flip-Flop.28 Sheet.24 D D Sheet.25 Q Q Standard Arrow.32 Standard Arrow.8 Standard Arrow.13 Arrow Standard Right.18 Arrow Standard Right.23 Arrow Standard Right.33 Sheet.33 Fast_Clock Fast_Clock Sheet.34 D Flip-Flop.38 Sheet.36 D D Sheet.37 Q Q Standard Arrow.42 Sheet.39 D Flip-Flop.44 Sheet.41 D D Sheet.42 Q Q Standard Arrow.48 Sheet.44 D Flip-Flop.50 Sheet.46 D D Sheet.47 Q Q Standard Arrow.54 Sheet.49 Sheet.50 Sheet.51 Sheet.57 reg0 reg0 Sheet.58 reg1_bret reg1_bret Sheet.59 reg2_bret reg2_bret Sheet.60 reg3_bret reg3_bret Sheet.61 reg4 reg4 Sheet.62 x-number text box X13430-041422 X13430-041422