Scenarios Preventing Block RAM Output Register Inference - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

Xilinx recommends that the memory and the output registers are all inferred in a single level of hierarchy, because this is the easiest method to ensure inference is as intended. There are two scenarios that will infer a block RAM output register. The first one is when an extra register exists on the output, and the second is when the read address register is retimed across the memory array. This can only happen using single port RAM. This is illustrated below:

Figure 1. RAM with Extra Read Register for Block RAM Output Register Inference

Figure 2. View of RAM Before Address Register Retiming

Certain deviations from these examples can prevent the inference of the output register.