Check Timing Report - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-11-19
Version
2021.2 English

The Check Timing report (multiple_clock) identifies the clock pins that are reached by more than one clock and a set_clock_groups or set_false_path constraint has not already been defined between these clocks.