SSI Pinout Considerations - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
Release Date
2021.2 English

When planning pinouts for components that are located in a particular SLR, place the pins into the same SLR. For example, when using the device DNA information as a part of an external interface, place the pins for that interface in the master SLR in which the DNA_PORT exists. Additional considerations include the following:

  • Group all pins of a particular interface into the same SLR.
  • For signals driving components in multiple SLRs, place those signals in the middle SLR.
  • Balance CCIO or CMT components across SLRs.
  • Reduce SLR crossings.