Routing (route_design) - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

The Vivado Design Suite router performs routing on the placed design and performs optimization on the routed design to resolve hold time violations. By default, the router performs optimization using a balance between runtime and design performance while alleviating congestion. Some router directives sacrifice runtime for better design performance and more aggressive congestion reduction. For more information on routing, see this link in the Vivado Design Suite User Guide: Implementation (UG904).