Synthesis Constraints and Attributes - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

A simple way to control clocking resources is to use the CLOCK_BUFFER_TYPE synthesis constraint or attribute. Synthesis constraints may be used to:

  • Prevent BUFG inference.
  • Replace a BUFG with an alternative clocking structure.
  • Specify a clock buffer where one would not exist otherwise.

Using synthesis constraints allows this type of control without requiring any modification to the code.

Attributes can be placed in either of the following locations:

  • Directly in the HDL code, which allows them to persist in the code
  • As constraints in the XDC file, which allows this control without any changes needed to the source HDL code