Power optimization works to minimize the impact on timing while maximizing power savings. However, in certain cases, if timing degrades after power optimization, you can employ a few techniques to offset this impact.
Where possible, identify and apply power optimizations only on non-timing
critical clock domains or modules using the set_power_opt XDC command. If the most critical clock domain happens to
cover a large portion of the design or consumes the most power, review critical paths to
see if any cells in the critical path have the IS_CLOCK_GATED property with value TRUE,
indicating that the paths are the result of a power optimization. To improve timing at
the expense of increased power in a subsequent implementation, use the set_power_opt XDC constraint to disable power optimization
on the power-optimized cells in the critical path. Then rerun implementation with the
set_power_opt XDC constraints or Tcl commands.
The following Tcl example disables power optimization on cells in the top 100 failing paths:
set pwr_critical_cells [get_cells -of [get_timing_paths -slack_lesser_than 0 -max_paths 100] -filter {IS_CLOCK_GATED}]
set_power_opt -exclude_cells $pwr_critical_cells