Tips for Control Signals - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
Release Date
2021.2 English
  • Check whether a global reset is really needed.
  • Avoid asynchronous control signals.
  • Keep clock, enable, and reset polarities consistent.
  • Do not code a set and reset into the same register element.
  • If an asynchronous reset is absolutely needed, remember to synchronize its deassertion.