Recommended Constraints Sequence - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

The constraints language (XDC) is based on Tcl syntax and interpretation rules. Like Tcl, XDC is a sequential language:

  • Variables must be defined before they can be used. Similarly, timing clocks must be defined before they can be used in other constraints.
  • For equivalent constraints that cover the same paths and have the same precedence, the last one applies.
  • When a path is covered by multiple timing exceptions, the constraint with the higher precedence applies.

When considering the priority rules above, the timing constraints should overall use the following sequence:

## Timing Assertions Section
# Primary clocks
# Virtual clocks
# Generated clocks
# Delay for external MMCM/PLL feedback loop
# Clock Uncertainty and Jitter
# Input and output delay constraints
# Clock Groups and Clock False Paths
## Timing Exceptions Section
# False Paths
# Max Delay / Min Delay
# Multicycle Paths
# Case Analysis
# Disable Timing

When multiple XDC files are used, you must pay particular attention to the clock definitions and validate that the dependencies are ordered correctly.

The physical constraints can be located anywhere in any constraint file.