report_qor_suggestions Tcl command flags this issue.In UltraScale devices, BUFGCE_DIV cells can be used to reduce clock uncertainty on synchronous clock domain crossings by eliminating MMCM Phase Error. For example, consider a path between a 300 MHz and 150 MHz clock domains, where both clocks are generated by the same MMCM.
In this case, the clock uncertainty includes 120 ps of Phase Error for both Setup and Hold analysis. Instead of generating the 150 MHz clock with the MMCM, a BUFGCE_DIV can be connected to the 300 MHz MMCM output and divide the clock by 2. For optimal results, the 300 MHz clock needs to also use a BUFGCE_DIV with BUFGCE_DIVIDE set to 1 to match the 150 MHz clock delay accurately, as shown in the following figure.
With the new topology:
- For setup analysis, clock uncertainty does not include the MMCM phase error and is reduced by 120 ps.
- For hold analysis, there is no more clock uncertainty (only for same edge hold analysis).
- The common node moves closer to the buffers, which saves some clock pessimism.
By applying the CLOCK_DELAY_GROUP constraint on the two clock nets, the clock paths will have matched routing.
report_qor_suggestions Tcl command provides these constraints.The following tables compare the clock uncertainty for setup and hold analysis of an UltraScale synchronous CDC timing path.
| Setup Analysis | MMCM Generated 150 MHz Clock | BUFGCE_DIV 150 MHz Clock | |
|---|---|---|---|
| Total System Jitter (TSJ) | 0.071 ns | 0.071 ns | |
| Discrete Jitter (DJ) | 0.115 ns | 0.115 ns | |
| Phase Error (PE) | 0.120 ns | 0.000 ns | |
| Clock Uncertainty | 0.188 ns | 0.068 ns | |
| Hold Analysis | MMCM Generated 150 MHz Clock | BUFGCE_DIV 150 MHz Clock | |
|---|---|---|---|
| Total System Jitter (TSJ) | 0.071 ns | 0.000 ns | |
| Discrete Jitter (DJ) | 0.115 ns | 0.000 ns | |
| Phase Error (PE) | 0.120 ns | 0.000 ns | |
| Clock Uncertainty | 0.188 ns | 0.000 ns | |