Propagation Limitations - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
Release Date
2021.2 English
Tip: For high-speed propagation across SLRs, be sure to register signals that cross SLR boundaries.

SLL signals are the only data connections between SLR components.

The following do not propagate across SLR components:

  • Carry chains
  • DSP cascades
  • Block RAM address cascades
  • Other dedicated connections, such as DCI cascades and block RAM cascades

The tools normally take this limit on propagation into account. To ensure that designs route properly and meet your design goals, you must also take this limit into account when you:

  • Build a very long DSP cascade and manually place such logic near SLR boundaries
  • Specify a pinout for the design