Reusing Placement Results - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID

UG949

Release Date

2021-11-19

Version

2021.2 English

It is fairly easy to reuse the placement of block RAM macros and DSP macros. Reusing this placement helps to reduce the variability in results from one netlist revision to the next. These primitives generally have stable names. The placement is usually easy to maintain. Some placement directives result in better block RAM and DSP macro placement than others. You can try applying this improved macro placement from one placer run to others using different placer directives to improve QoR. Following is a simple Tcl script that saves block RAM placement into an XDC file for UltraScale and UltraScale+ device designs.

set_property IS_LOC_FIXED 1 \
  [get_cells -hier -filter {PRIMITIVE_TYPE =~ BLOCKRAM.*.*}] 
write_xdc bram_loc.xdc -exclude_timing

You can edit the bram_loc.xdc file to only keep block RAM location constraints and apply it for your consecutive runs.

Important: Do not reuse the placement of general slice logic. Do not reuse the placement for sections of the design that are likely to change. Use the Incremental Compile flow if you make small changes to the design and want to re-use prior placement to achieve more predictable results and faster compile time.