In the Vitis™ environment, you can specify the hardware kernel as a C/C++ kernel or as an RTL kernel:
- When using a C/C++ kernel, you must specify additional user constraints for synthesis or implementation using Vitis HLS. The Vitis HLS output must then be packaged in the IP packager, and this packaged IP includes both the user and tool-generated constraints. For information, see the Vitis HLS User Guide (UG1399).
- When using an RTL kernel, you must specify additional synthesis and implementation constraints during IP packaging. For information, see the Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118).
In the Vitis environment, all of the design constraints for synthesis and implementation must be packaged with the IP. If additional constraints are required for synthesis after the IP is packaged, you must repackage the IP to include the missing constraints.
However, after the IP is packaged, you can specify additional XDC constraints
to be used only during implementation. Although the Vitis environment abstracts the underlying Vivado tools process for implementing the programmable logic region, the
Vitis environment also provides advanced options
to control the Vivado tools flow. With these advanced controls, you can specify certain Tcl
scripts to be executed before (Pre) or after (Post) each implementation phase,
including the following: init_design
, opt_design
, place_design
, phys_opt_design
, route_design
, or write_bitstream
.
For more information
on Tcl scripting, see the
Vivado
Design Suite User Guide: Using Tcl Scripting (UG894). You
can leverage the Pre and Post Tcl scripts to execute certain Vivado tools commands, such as to apply additional XDC constraints
through the read_xdc
or source
Tcl commands.
You can specify the Pre and Post Tcl scripts either through the Vitis environment configuration file or directly on the v++ compiler command line.
To specify the Pre and Post Tcl scripts inside the Vitis environment configuration file, use the parameters prop=run.impl_1.STEP.<PHASE>.TCL.<PRE|POST>
inside
the [vivado]
section.
Where:
-
<PHASE>
specifies the implementation phase:INIT_DESIGN
,OPT_DESIGN
,PLACE_DESIGN
,PHYS_OPT_DESIGN
,ROUTE_DESIGN
, orWRITE_BITSTREAM
. -
PRE
executes the script before the specified implementation phase. -
POST
executes the script after the specified implementation phase.
For example:
[vivado]
prop=run.impl_1.STEPS.OPT_DESIGN.TCL.PRE=<pathToTclScript>
prop=run.impl_1.STEPS.OPT_DESIGN.TCL.POST=<pathToTclScript>
prop=run.impl_1.STEPS.PLACE_DESIGN.TCL.PRE=<pathToTclScript>
prop=run.impl_1.STEPS.PLACE_DESIGN.TCL.POST=<pathToTclScript>
prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.TCL.PRE=<pathToTclScript>
prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.TCL.POST=<pathToTclScript>
prop=run.impl_1.STEPS.ROUTE_DESIGN.TCL.PRE=<pathToTclScript>
prop=run.impl_1.STEPS.ROUTE_DESIGN.TCL.POST=<pathToTclScript>
To specify the Pre and Post Tcl scripts as a v++ parameter, use the
--vivado.prop
run.impl_1.STEP.<PHASE>.TCL.<PRE|POST>=<pathToTclScript>
command
line option. For example, to specify a Tcl script to be executed before
opt_design
:
--vivado.prop run.impl_1.STEP.OPT_DESIGN.TCL.PRE=<pathToTclScript>
Where:
-
--vivado
is the v++ command line option to specify directives for the Vivado tools. -
prop
indicates a property setting. -
run.
indicates a run property. -
impl_1.
indicates the name of the run. -
STEP.OPT_DESIGN.TCL.PRE
indicates the run property you are specifying. -
<pathToTclScript>
indicates the property value.