You can force control set mapping by applying the DIRECT_RESET / DIRECT_ENABLE / EXTRACT_RESET / EXTRACT_ENABLE attributes as needed to handle the mapping of control sets for a given structure.
When the design includes a synchronous reset/enable, synthesis creates a logic cone
mapped through the CE/R/S pins when the load is equal to or above the threshold set
by the -control_set_opt_threshold synthesis switch,
or creates a logic cone that maps through the D pin if below the threshold. The
default thresholds are:
- 7 series devices: 4
- UltraScale devices: 2