Pre- and Post-Physical Optimization - 2021.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2021.2 English

Evaluate the need for running physical optimization to fix timing problems related to:

  • Nets with high fanout (report_high_fanout_nets shows highest fanout non-clock nets)
  • Nets with drivers and loads located far apart
  • Digital signal processor (DSP) and block RAM with sub-optimal pipeline register usage