Using Intelligent Design Runs - 2021.2 English - UG949

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs
Document ID
UG949
Release Date
2021-11-19
Version
2021.2 English

To automatically address most timing closure challenges during implementation, you can use an Intelligent Design Run (IDR). An IDR is a special type of implementation run that leverages report_qor_suggestions, ML-based strategy predictions, and incremental compile. An IDR can run up to 6 iterations of place and route, which leads to a typical compile time of 4.5 times that of a standard run. However, using IDR can provide significant benefits by reducing the knowledge required to close timing and by saving hours of user analysis.

Recommended: Because an IDR takes longer than a standard implementation run, Xilinx recommends using IDRs less frequently than standard runs. For example, use an IDR after you resolve all methodology warnings and after trying a few common implementation strategies, such as default and explore.
Tip: To iterate more quickly, you can extract the QoR suggestions and ML strategies from the IDR for use in a standard implementation run. If a significant design change is made, rerun the IDR to update the associated files.
An IDR comprises the following stages:
  1. Uses report_qor_suggestions to apply optimization properties to elements in the design in a predetermined order.
  2. Uses machine learning (ML) strategies to generate tool options for opt_design, place_design, phys_opt_design, and route_design that are optimized for the design.
  3. Uses a Last Mile Timing Closure feature to apply extensive effort on paths that are difficult to resolve to get the final result.

To ensure success when using IDR, follow these requirements:

  • The implementation must be project based. For non-project users, the easiest method is to create a post-synthesis netlist-based project using a pre-opt_design checkpoint.
  • The device must be from either an UltraScale or UltraScale+™ - device-based family.
  • The design must have a baseline with accurate and achievable constraints.
  • All designs must comply with the recommended methodology, as reported by the report_methodology Tcl command.
  • An SLR-based floorplan might be required for SSI technology-based devices.
  • Apply only automatic implementation suggestions. Text-based suggestions or suggestions with APPLICABLE_FOR = synth_design must be applied before starting an IDR.

For more information see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).