The following table shows the revision history for this document.
Section | Revision Summary |
---|---|
11/19/2021 Version 2021.2 | |
Reduce the Number of Partition Pins | Added PPLOC examples and graphics. |
Make Pblocks as Rectangular as Possible to Avoid Unroutability at the Edges | Updated examples. |
Incremental Synthesis | Added information on different modes. |
ML Strategies | Added non-project mode description and ML strategy suggestions. |
Connecting a Net to a Free External Pin Using Post-Route ECO | Updated section. |
08/18/2021 Version 2021.1 | |
Power Distribution System | Added XPE landing page and changed XADC to Sysmon. |
Power Rail Consolidation Impacting Power | Added tip about power rail constraints. |
Clocking Recommendations for Platforms and Dynamic Function eXchange | Added new section. |
Design Constraints | Added note about traditional and platform-based design flows. |
Constraining Input and Output Ports | Added note about I/O logic. |
Defining Power and Thermal Constraints | Added new section. |
Floorplanning Constraints for Dynamic Function eXchange | Added new section. |
Design Closure | Updated design closure description. |
Timing Closure | Added timing result note. |
Checking for Valid Constraints | Added baselining design to note. |
Checking for Positive Timing Slacks | Updated timing score description. |
Checking That Your Design is Properly Constrained | Added timing constraint note. |
Fixing Issues Flagged by report_methodology | Added methodology violation note and link to methodology blog. |
Methodology DRCs with Impact on Timing Closure | Added link to Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906). |
Assessing the Maximum Frequency of the Design | Updated WNS description. |
Clock Skew and Uncertainty | Added clock uncertainty description and related links. |
Using Intelligent Design Runs | Added new section. |
Power Closure | Added power optimization capabilities description. |
Power Timing Slack | Added new section. |