The final step in the Vitis HLS
design flow is to package and export the RTL output. Click the Export RTL toolbar button or click
to open the Export RTL dialog
box shown in the following figure.
The final step in the Vitis HLS flow is to export the RTL design in a form that can be used by other tools in the Xilinx design flow. The RTL design can be packaged into the following output formats:
Format Selection | Subfolder | Comments |
---|---|---|
Vivado IP (.zip) |
solution/impl/export.zip
|
The IP is exported as a ZIP file that can be added to the Vivado IP catalog. The |
Vitis Kernel (.xo) |
solution/impl/export.xo
|
The XO file output can be used for linking by the Vitis compiler in the application acceleration development flow. You can link the Vitis kernel with other kernels, and the target accelerator card, to build the xclbin file for your accelerated application. |
Synthesized Checkpoint (.dcp) |
solution/impl/ip
|
This option creates Vivado checkpoint files which can be added directly into a design in the Vivado Design Suite. This option requires RTL synthesis to be performed.
When this option is selected, the The output includes an HDL wrapper you can use to instantiate the IP into a higher level design. |
Vivado IP for System Generator |
solution/impl/ip
|
This option creates IP for use with the Vivado edition of System Generator for DSP. |
Finally, you can also specify the output location to write the export file to. If the location is not specified, the default location is the solution/impl/ folder of the project.