s_axilite interface. Only the default assignments are
supported.s_axilite interface.
Port-level I/O protocols sequence data into and out of the HLS engine from
the s_axilite adapter as seen in S_AXILITE Example. The tool assigns a
default port protocol to a port depending on the type and direction of the
argument associated with it. The port can contain one or more of the
following: - Data signal for the argument
- Valid signal (
ap_vld/ap_ovld) to indicate when the data can be read - Acknowledge signal (
ap_ack) to indicate when the data has been read
The default port protocol assignments for various argument types are as follows:
| Argument Type | Default | Supported |
|---|---|---|
| scalar |
ap_none
|
ap_ack and ap_vld can also be used |
| Pointers/References | ||
| Inputs |
ap_none
|
ap_ack and ap_vld
|
| Outputs |
ap_vld
|
ap_none, ap_ack, and ap_ovld can also be used |
| Inouts |
ap_ovld
|
ap_none, ap_ack, and ap_vld are also supported |
ap_memory. The bram port
protocol is not supported for arrays in an s_axilite interface.The example groups port b
into the s_axilite interface and specifies
port b as using the ap_vld protocol with
INTERFACE pragmas. As a result, the s_axilite adapter contains a register for the port b data, and a register for the port b input valid signal.
If the input valid register is not set to logic 1, the data in
the b data register is not considered
valid, and the design stalls and waits for the valid register to be set.
Each time port b is read, Vitis HLS automatically clears the input
valid register and resets the register to logic 0.
s_axilite interface.