ap_return
for the return value. s_axilite
) all the ports in the block-level interface are grouped into the
s_axilite
interface. This is a common practice when
another device, such as a CPU, is used to configure and control when the block starts and
stops operation, and is a requirement of XRT.The ap_ctrl_hs
block-level I/O protocol is
the default for the Vivado IP flow. Default Interfaces for Vivado IP Flow shows the resulting RTL ports and behavior when
Vitis HLS implements ap_ctrl_hs
on a function.
The ap_ctrl_chain
control protocol is
similar to ap_ctrl_hs
but provides an additional input
signal ap_continue
to apply back pressure. Xilinx recommends using the ap_ctrl_chain
block-level I/O protocol when chaining Vitis HLS blocks together and is the default for the Vitis Kernel flow. Refer to Supported Kernel Execution Models for more information on how XRT
uses these control protocols.
ap_ctrl_hs
The following figure shows the behavior of the block-level handshake
signals created by the ap_ctrl_hs
I/O protocol for a
non-pipelined design.
After reset, the following occurs:
- The block waits for
ap_start
to go High before it begins operation. - Output
ap_idle
goes Low immediately to indicate the design is no longer idle. - The
ap_start
signal must remain High untilap_ready
goes High. Onceap_ready
goes High:- If
ap_start
remains High the design will start the next transaction. - If
ap_start
is taken Low, the design will complete the current transaction and halt operation.
- If
- Data can be read on the input ports.
- Data can be written to the output ports.Note: The input and output ports can also specify a port-level I/O protocol that is independent of this block-level I/O protocol. For details, see Port-Level I/O Protocols.
- Output
ap_done
goes High when the block completes operation.Note: If there is anap_return
port, the data on this port is valid whenap_done
is High. Therefore, theap_done
signal also indicates when the data on outputap_return
is valid. - When the design is ready to accept new inputs, the
ap_ready
signal goes High. Following is additional information about theap_ready
signal:- The
ap_ready
signal is inactive until the design starts operation. - In non-pipelined designs, the
ap_ready
signal is asserted at the same time asap_done
. - In pipelined designs, the
ap_ready
signal might go High at any cycle afterap_start
is sampled High. This depends on how the design is pipelined. - If the
ap_start
signal is Low whenap_ready
is High, the design executes untilap_done
is High and then stops operation. - If the
ap_start
signal is High whenap_ready
is High, the next transaction starts immediately, and the design continues to operate.
- The
- The
ap_idle
signal indicates when the design is idle and not operating. Following is additional information about theap_idle
signal:- If the
ap_start
signal is Low whenap_ready
is High, the design stops operation, and theap_idle
signal goes High one cycle afterap_done
. - If the
ap_start
signal is High whenap_ready
is High, the design continues to operate, and theap_idle
signal remains Low.
- If the
ap_ctrl_chain
The ap_ctrl_chain
block-level I/O
protocol is similar to the ap_ctrl_hs
protocol but
provides an additional input port named ap_continue
. An
active-High ap_continue
signal indicates that the
downstream block that consumes the output data is ready for new data inputs. If the
downstream block is not able to consume new data inputs, the ap_continue
signal is Low, which prevents upstream blocks from generating
additional data.
The ap_ready
port of the downstream
block can directly drive the ap_continue
port. Following
is additional information about the ap_continue
port:
- If the
ap_continue
signal is High whenap_done
is High, the design continues operating. The behavior of the other block-level I/O signals is identical to those described in theap_ctrl_hs
block-level I/O protocol. - If the
ap_continue
signal is Low whenap_done
is High, the design stops operating, theap_done
signal remains High, and data remains valid on theap_return
port if theap_return
port is present.
In the following figure, the first transaction completes, and the second
transaction starts immediately because ap_continue
is High
when ap_done
is High. However, the design halts at the end
of the second transaction until ap_continue
is asserted
High.
ap_ctrl_none
If you specify the ap_ctrl_none
block-level I/O protocol, the handshake signal ports (ap_start
, ap_idle
, ap_ready
, and ap_done
) are not created. You
can use this protocol to create a block without control signals, as used in free-running
kernels.
ap_ctrl_none
block-level I/O protocol on your design,
you must meet at least one of the conditions for C/RTL co-simulation as described in Interface Synthesis Requirements to verify the RTL
design. If at least one of these conditions is not met, C/RTL co-simulation halts with the
following
message:@E [SIM-345] Cosim only supports the following 'ap_ctrl_none' designs: (1)
combinational designs; (2) pipelined design with task interval of 1; (3) designs with
array streaming or hls_stream ports.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***