Default Interfaces for Vivado IP Flow - 2020.2 English

The Vivado IP flow supports a wide variety of I/O protocols and handshakes due to the requirement of supporting FPGA design for a wide variety of applications. This flow implements the following interfaces by default:

• Scalar inputs: ap_none interface mode
• Array: ap_memory interface mode
• Pointers or Reference:
  • Input: ap_none interface mode
  • InOut: ap_ovld interface mode
  • Output: ap_vld interface mode
• Arguments specified as hls::stream: ap_fifo interface mode
• Function Return: ap_return port using the ap_none interface mode
• Block Protocol: ap_ctrl_hs

The sum_io function in the following code provides an example of interface synthesis.

#include "sum_io.h"

dout_t sum_io(din_t in1, din_t in2, dio_t *sum) {

 dout_t temp;

 *sum = in1 + in2 + *sum;
 temp = in1 + in2;

 return  temp;
}

The sum_io function includes:

• Two pass-by-value inputs: in1 and in2.
• A pointer: sum that is both read from and written to.
• A function return assigned the value of temp.

With the default interface synthesis settings used for the Vivado IP flow, the design is synthesized into an RTL block with the ports and interfaces shown in the following figure.

Figure 1. RTL Ports After Default Interface Synthesis

In the default Vivado IP flow the tool creates two types of interface ports on the RTL design to handle the flow of both data and control.

• Block-level interface protocol: The ap_ctrl interface in the preceding figure has been expanded to show the signals provided by the default ap_ctrl_hs protocol: ap_start, ap_done, ap_ready, and ap_idle.
• Port-level interface protocols: These are created for each argument in the top-level function and the function return (if the function returns a value). As explained above most of the arguments use a port protocol of ap_none, and so have no control signals. In the sum_io example above these ports include: in1, in2, sum_i, and ap_return. However, the output port uses the ap_vld protocol and so the sum_o output is associated with the sum_o_ap_vld signal.
  Note: Notice that the inout argument, sum, has been split into input and output ports.