The Vitis kernel flow provides support for compiled kernel objects (.xo) for control by the Xilinx Run Time (XRT) and integration with a host application. This flow has very specific interface requirements that Vitis HLS must meet. This flow implements the following interfaces by default:
- Scalar inputs: AXI4-Lite interface
(
s_axilite
) - Pointers to an Array: AXI4 memory
mapped interface (
m_axi
) to access the memory, and thes_axilite
interface to receive the offset into the memory address space. - Arguments specified as
hls::stream
: AXI4-Stream interface (axis
) - Function Return:
ap_return
port added to thes_axilite
interface - Block Protocol:
ap_ctrl_chain
specified on thes_axilite
interface.
The s_axilite
interface is special in
the Vitis kernel flow. It handles the input of scalar
arguments from the software function into the kernel as well as any function return value;
but it also specifies offsets for m_axi
interfaces and
handles the block control protocol.
The sum_io
function in the following
code provides an example of interface synthesis.
#include "sum_io.h"
dout_t sum_io(din_t in1, din_t in2, dio_t *sum) {
dout_t temp;
*sum = in1 + in2 + *sum;
temp = in1 + in2;
return temp;
}
The sum_io
function includes:
- Two pass-by-value inputs:
in1
andin2
. - A pointer:
sum
that is both read from and written to. - A function
return
assigned the value oftemp
.
With the default interface synthesis settings used by Vitis HLS for the Vivado IP flow, the design is synthesized into an RTL block with the ports and interfaces shown in the following figure.
In the default Vitis kernel flow the tool creates three types of interface ports on the RTL design to handle the flow of both data and control.
- Clock, Reset, and Interrupt ports:
ap_clk
andap_rst_n
andinterrupt
are added to the kernel. -
AXI4-Lite interface:
s_axi_control
interface to handle data values for scalar argumentsin1
andin2
, and to handle the functionreturn
value. The interface is expanded to show the various ports associated with it. -
AXI4 memory mapped interface:
m_axi_gmem
interface to handle thesum
argument. - Block-Level interface protocol: The default
ap_ctrl_chain
protocol is associated with thes_axi_control
interface.