Description
The BIND_STORAGE pragma assigns a variable (array, or function argument)
in the code to a specific memory type (type
) in the RTL.
If the pragma is not specified, the Vitis HLS tool
determines the memory type to assign. The HLS tool implements the memory using specified
implementations (impl
) in the hardware.
For example, you can use the pragma to specify which memory type to use to implement an array. This lets you control whether the array is implemented as a single or a dual-port RAM for example. This usage is important for arrays on the top-level function interface, because the memory type associated with the array determines the number and type of ports needed in the RTL, as discussed in Arrays on the Interface.
You can also specify the latency of the implementation. For block RAMs on
the interface, the latency
option lets you model off-chip,
non-standard SRAMs at the interface, for example supporting an SRAM with a latency of 2 or
3. For internal operations, the latency
option allows the
memory to be implemented using more pipelined stages. These additional pipeline stages can
help resolve timing issues during RTL synthesis.
latency
option, the operation must have an available
multi-stage implementation. The HLS tool provides a multi-stage implementation for all block
RAMs.Syntax
Place the pragma in the C/C++ source within the body of the function where the variable is defined.
#pragma HLS bind_storage variable=<variable> type=<type>\
[ impl=<value> latency=<int> ]
Where:
-
variable=<variable>
- Defines the variable to assign the BIND_STORAGE pragma to. This is required when specifying the pragma.
-
type=<type>
- Defines the type of memory to bind to the specified variable.
-
impl=<value>
- Defines the implementation for the specified memory type. Supported
implementations include:
bram
,bram_ecc
,lutram
,uram
,uram_ecc
, andsrl
as described below. -
latency=<int>
- Defines the default latency for the binding of the type. As shown in
the following table, the valid latency varies according to the specified
type
andimpl
. The default is -1, which lets Vitis HLS choose the latency.
Type | Implementation | Min Latency | Max Latency |
---|---|---|---|
FIFO | MEMORY | 0 | 0 |
FIFO | BRAM | 0 | 0 |
FIFO | LUTRAM | 0 | 0 |
FIFO | SRL | 0 | 0 |
FIFO | URAM | 0 | 0 |
RAM_1P | AUTO | 1 | 3 |
RAM_1P | BRAM | 1 | 3 |
RAM_1P | LUTRAM | 1 | 3 |
RAM_1P | URAM | 1 | 3 |
RAM_1WnR | AUTO | 1 | 3 |
RAM_1WnR | BRAM | 1 | 3 |
RAM_1WnR | LUTRAM | 1 | 3 |
RAM_1WnR | URAM | 1 | 3 |
RAM_2P | AUTO | 1 | 3 |
RAM_2P | BRAM | 1 | 3 |
RAM_2P | LUTRAM | 1 | 3 |
RAM_2P | URAM | 1 | 3 |
RAM_S2P | BRAM | 1 | 3 |
RAM_S2P | BRAM_ECC | 1 | 3 |
RAM_S2P | LUTRAM | 1 | 3 |
RAM_S2P | URAM | 1 | 3 |
RAM_S2P | URAM_ECC | 1 | 3 |
RAM_T2P | BRAM | 1 | 3 |
RAM_T2P | URAM | 1 | 3 |
ROM_1P | AUTO | 1 | 3 |
ROM_1P | BRAM | 1 | 3 |
ROM_1P | LUTRAM | 1 | 3 |
ROM_2P | AUTO | 1 | 3 |
ROM_2P | BRAM | 1 | 3 |
ROM_2P | LUTRAM | 1 | 3 |
ROM_nP | BRAM | 1 | 3 |
ROM_nP | LUTRAM | 1 | 3 |
Memory Type | Unsupported Implementation |
---|---|
FIFO | URAM |
RAM_1P | SRL |
RAM_2P | SRL |
RAM_S2P | SRL |
RAM_T2P | SRL, LUTRAM |
RAM_1WnR | SRL |
ROM_1P | SRL, URAM |
ROM_2P | SRL, URAM |
ROM_nP | SRL, URAM |
Example
In the following example, the coeffs[128]
variable is an argument to the top-level function foo_top
.
The pragma specifies that coeffs
uses a single port RAM
implemented on a BRAM.
#pragma HLS bind_storage variable=coeffs type=RAM_1P impl=bram
coeffs
are defined in the
RAM_1P.