Tutorial Requirements - 2024.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Release Date
2024-06-12
Version
2024.1 English

The design supplied here specifically targets the VCK190 (and its Versal AI Core VC1902 device) development system. The entire design can be processed completely or partially via scripts. The VMK180 (and its Versal Prime VM1802 device) could also be targeted by changing the part and board references in the project creation script, but this design has not been tested in that hardware. The key scripts found in the project archive are as follows:

run_all.tcl
This script runs the entire flow from block design creation to bitstream generation and hardware export. This includes all the steps managed by the DFX Wizard. It calls multiple scripts, in the following order:
  1. create_top_bd.tcl – This script creates the static block design and all IP for a completely flat design. One could run this script and then launch the implementation to generate a standard (non-DFX) implementation for the VCK190
  2. create_rp1_bdc.tcl – This script creates two levels of hierarchy and converts one to be a block design container.
  3. enable_dfx_bdc.tcl – This script turns the standard BDC into a DFX BDC.
  4. create_rp1rm2.tcl – This script creates a new RM for the existing DFX BDC.
  5. run_impl.tcl – This script is the remainder of the flow. This script creates a top-level wrapper, adds design constraints, and walks through the DFX Wizard. It then generates all outputs for the design, from IP results to synthesis and implementation runs, then creates bitstreams and XSA files for hardware handoff.

This tutorial can be run completely via a script by sourcing the run_all.tcl script in a Vivado Tcl shell. Each sub-section can also be run individually using the remaining Tcl scripts listed above. The tutorial as described manually runs through most steps to show what is happening throughout the flow. Sub-section scripts are noted along the way. This tutorial does not show iterative interaction with the IP integrator design.