Step 5: Add a New Reconfigurable Module - 2024.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Release Date
2024-06-12
Version
2024.1 English

Dynamic Function eXchange would not be very compelling without multiple Reconfigurable Modules (RM) to swap between, so the next step is to create a new RM for the RP that now exists.

Follow the instructions below or source create_rp1rm2.tcl to automate the steps.

  1. Right-click on the rp1 instance and select Create Reconfigurable Module. In the dialog box that opens, give the RM a name of rp1rm2 and click OK.

    A new block design is created and opened. The diagram consists of three input pins, which are the same port list as the first RM for the rp1 partition. The port list for each RM for a given RP must be identical, even if not all of the ports are used by each RM.
    Note: In the log and script the create_bd_design command uses the -boundary_from_container option, copying the explicit port list from the block design container.
  2. Add a new IP to the canvas by clicking the + icon and using the search field to find the AXI GPIO IP. Add it to the canvas, then double-click to customize. Check the All Inputs box for GPIO, ensure the GPIO Width is set to 32, then OK to return to the canvas.

  3. Click the + again and use the search field to add a Constant IP to the canvas. Double-click to customize. Change the Const Width to 32 and Const Val to 0xFACEFEED. Click OK to accept the edits.

  4. Click the + again and use the search field to add an AXI SmartConnect IP to the canvas. Double-click to customize. Change the Number of Slave Interfaces to 1 so that all values are now 1. Click OK to accept the edits.

  5. Click the + one last time and use the search field to add an AXI NoC IP to the canvas. Double-click to customize. Under the General tab, set the Number of AXI Slave Interfaces to 0 and the Number of Inter-NOC Slave Interfaces to 1. On the Connectivity tab, check the single box to connect M00_AXI to S00_INI. Click OK to accept the edits.

    The Inter-NoC Interface (INI) provides a means of connecting two NoC instances. An INI link represents a logical connection within the physical NoC that is resolved at the time the NoC compiler is called. The boundary between static and reconfigurable sections of the NoC must be done using INI ports – note there is a corresponding AXI NoC IP with an Inter-NOC Master Interface in the static design.

  6. Connect the pins to create the diagram as shown in following figure.
    Note: You need to expand the GPIO port to expose the 32-bit input bus to match the type of the Constant dout bus. Regenerate the layout to make it look nice.


  7. Switch to the Address Editor window and see that no addresses are assigned. Right-click the row for /axi_gpio_0/S_AXI and select Assign. This sets a 64K range starting at address 0x0000_0202_0000_0000.
  8. Modify the Master Base Address so it starts at 0x0201_8001_0000 then keep the Range at 64K.

  9. Back in the block design, click Validate Design and then Save to save the rp1rm2 block design.

    In this simple design, there are only two differences between rp1rm1 and rp1rm2:

    1. The S_AXI base addresses are different.
    2. The constant values that can be read via GPIO are different.

    This first difference is used to show that device tree overlays must be created and managed for designs that might have different requirements between Reconfigurable Modules. The second difference is used to confirm that dynamic reconfiguration in hardware has been done successfully.