Bitstream Creation - 2024.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Release Date
2024-06-12
Version
2024.1 English

The Nested DFX design methodology moves the HD.RECONFIGURABLE property down and up through the hierarchy. Implementation tools follow standard DFX design rules based on what cells are currently defined as reconfigurable. This holds true for write_bitstream as well; partial bitstreams will only be created for cells currently holding the HD.RECONFIGURABLE property.

With any fully routed design checkpoint open in Vivado, use write_bitstream to generate full and partial bitstreams. Remember, by default this command will generate a standard full bitstream for the entire device and a partial bitstream for each cell currently defined as a Reconfigurable Partition. Two options can limit results to one or the other:

  • The -cell option will generate ONLY a partial bitstream for the requested cell.
  • The -no_partial_bitfile option will generate ONLY a standard full device bitstream
Run the following script to create a collection of full and partial bitstreams for existing configurations that have been implemented. To save time and space, only a single full device bitstream is created.
source generate_all_bitstreams.tcl

This script opens each checkpoint, one by one, and writes specific full or partial bitstreams. The bitstreams are placed in subfolders based on compatibility. Each bitstream is created with either the -no_partial_bitfile option (the first bitstream listed below) or the -cell option (every other bitstream). The use of the latter means that partial bit file names can be anything you desire; use names that clearly indicate function, version and compatibility. Here are the eleven bitstreams generated in their respective folders:

  • Bitstreams
    • top_shift_right_right.bit
  • Bitstreams/inst_RP
    • inst_RP_shift_right_right_recombined_partial.bit
    • inst_RP_count_up_up_recombined_partial.bit
  • Bitstreams/inst_shift
    • shift_right_upper_partial.bit
    • shift_right_lower_partial.bit
    • shift_left_upper_partial.bit
    • shift_left_lower_partial.bit
  • Bitstreams/inst_count
    • count_up_upper_partial.bit
    • count_up_lower_partial.bit
    • count_down_upper_partial.bit
    • count_down_lower_partial.bit

In addition to these, clearing bit files are created for UltraScale devices, one for each partial bit file listed above. The base names are the same but end in “_clear.” More information about how these are to be used is given in the next section of this lab.

Commands are also included to create, implement, and generate partial bitstreams for grey box configurations. These are not required for the solution but can be used to “turn off” activity within a particular RP. Set the grey parameter to “true” before sourcing the generate_all_bitstreams.tcl script to create these optional partial bitstreams.

Grey box partial (and clearing) bitstreams are established for each second-order RP (4 in total) and the first-order RP (inst_RP), as well as the case of each inst_RP RM instance (reconfig_shifters, reconfig_counters) with grey boxes for the second-order RPs within them.
  • Bitstreams/inst_RP
    • inst_RP_grey_partial.bit
    • reconfig_shifters_grey_grey_partial.bit
    • reconfig_counters_grey_grey_partial.bit
  • Bitstreams/inst_shift
    • shift_upper_grey_partial.bit
    • shift_lower_grey_partial.bit
  • Bitstreams/inst_count
    • count_upper_grey_partial.bit
    • count_lower_grey_partial.bit

Note that no bitstreams have been created from the initial top_route_design.dcp checkpoint. This is because there is no need – the top-level static image for this design is identical to all others, and the shift_right-shift_right function is logically the same to the first subdivided run. The implementation results for the latter are different because of the new RPs introduced, but if you were to load a shift_right-shift_right partial image from before the subdivide, you could not individually swap out the second-order shifters.

For this lab a full device bitstream is created only for this shift_right-shift_right version of the design, but a full device bitstream could be generated for any legal combination of first- and second-order Reconfigurable Modules. It simply depends on how you would like the device to initially behave. You could create a count_up-count_down version, or a shifter version with grey boxes for each second-order RP, all by linking routed module checkpoints with the locked top static, then calling write_bitstream.

In summary, build the design results from the top down, locking each relative static layer using the pr_subdivide function. Then, to return to higher-level Reconfigurable Partitions, use pr_recombine to create checkpoints for generating partial bitstreams at that level.