Step 5: Building the Design Floorplan - 2024.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

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2024.1 English

Next, create a floorplan to define the regions that are to be partially reconfigured.

  1. Select the inst_count instance in the Netlist window. Right-click and select Floorplanning > Draw Pblock, or select the Draw Pblock toolbar button, and draw a tall narrow box on the left side of the X0Y3 clock region. The exact size and shape do not matter at this point, but keep the box within the clock region.

    Make sure that the Pblock is selected in the Device window before continuing.

    Although this Reconfigurable Module only requires CLB resources, it also includes RAMB18, RAMB36, or DSP48 resources if the box encompasses those types. This allows the routing resources for these block types to be included in the reconfigurable region. The General view of the Pblock Properties window can be used to add these if needed. The Statistics view shows the resource requirements of the currently loaded Reconfigurable Module.

  2. In the Properties view, select the checkbox for RESET_AFTER_RECONFIG to use the dedicated initialization of the logic in this module after reconfiguration completes.
  3. Repeat steps 1 and 2 for the inst_shift instance, this time targeting the right side of clock region X1Y1. This Reconfigurable Module includes block RAM instances, so the resource type must be included. If omitted, the RAMB details in the Statistics view are shown in red.

  4. Run DFX Design Rule Checks by selecting Reports > Report DRC. You can uncheck All Rules and then check Dynamic Function eXchange to focus this report strictly on DFX DRCs.

    One or two DRCs are reported at this point, and there are two ways of resolving them. For this lab, use one method for inst_shift and the other for inst_count.

    The first DRC is an error, HDPR-10, reporting that RESET_AFTER_RECONFIG requires Pblock frame alignment.

  5. To resolve the first DRC error, make sure that the height of the Pblock aligns with the clock region boundaries. Using the Pblock for inst_shift, stretch the top and bottom edges to match the clock region boundaries of X1Y1 as shown in the following figure. See that the shading of the Pblock is now more uniform.

    The other possible DRC is a warning, HDPR-26, reporting that a left or right edge of a reconfigurable Pblock terminates on an improper boundary. Left or right edges must not split interconnect (INT) columns. For more information on this requirement, see the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

  6. To manually avoid this DRC warning, zoom into the upper or lower corner on the reported edge of inst_shift (or inst_count, if inst_shift did not report an issue) to see where the violation occurred. Move this edge left or right one column, as shown by the yellow arrows in the following figure so it lands between two resource types (CLB-CLB or CLB-RAMB, for example) instead landing between CLB-INT or RAMB-INT.

  7. Run the PR DRCs again to confirm that the errors and warnings that you have addressed have been resolved for the inst_shift instance.

    An alternative to manually adjusting the size and shape of reconfigurable Pblocks is to use the SNAPPING_MODE feature. This feature automatically adjusts edges to align with legal boundaries. It will make the Pblock taller, aligning with clock region boundaries, if the RESET_AFTER_RECONFIG feature is selected. It makes the Pblock narrower, adjusting left and/or right edges as needed. Note that the number and type of resources available are altered if SNAPPING_MODE makes changes to the Pblock.

  8. Select the Pblock for inst_count in the Device window, and in the Properties view of the Pblock Properties window, change the value of SNAPPING_MODE from OFF to ROUTING (or ON).
    Note: The original Pblock does not change, but the shading behind it does. The adjustments to the Pblock needed for it to conform to DFX rules are done automatically, without modifying your source constraints.
  9. Run the DFX DRCs once again to confirm that all errors have been resolved. Advisory messages might still be reported, especially if the Pblock is located near the edge of the device.
  10. Save these Pblocks and associated properties:
    write_xdc ./Sources/xdc/top_all.xdc

    This exports all the current constraints in the design, including those imported earlier from top_io_$board.xdc. These constraints can be managed in their own XDC file or managed within a run script (as is typically done with HD.RECONFIGURABLE).

    Alternatively, the Pblock constraints themselves can be extracted and managed separately. A Tcl proc is available to help perform this task.

    1. Source the proc which is found in one of the Tcl utility files:
      source ./Tcl_HD/hd_utils.tcl
    2. Use the export_pblocks proc to write out this constraint information:
      export_pblocks -file ./Sources/xdc/pblocks.xdc

      This writes the Pblock constraint information for both Pblocks in the design. Use the -pblocks option to select only one if desired.

      Now that the floorplan is established, the next step is implementing the design.