Step 11: Connecting to the Board and Programming the FPGA - 2024.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Release Date
2024-06-12
Version
2024.1 English
  1. Open the hardware manager and connect to the target board.

    This can be a local board or on a remote server. Exact details of how to accomplish this task depends on your setup. You can interact with this design remotely via the VIO and ILA debug cores.

  2. Once you are connected to the hardware, right-click on the FPGA instance and select Program Device. The top.bit file should be selected by default from the project_1.runs/impl_1 directory. If it is not, select top.bit from the impl_1 project run directory. Note that the top.ltx probes file is automatically selected. This is a complete device bitstream that includes the multiplier RM.
  3. Click on the hw_vio_1 dashboard tab. If it is not visible, open Dashboard Options and check the hw_vio_1 box.
  4. Press the + button and select all the probes from the Add Probes dialog box, then click OK.

  5. Right-click on the probes and set them up in the following manner:
    • count_out_OBUF[7:0] bus – Radix: unsigned decimal
    • count_out_OBUF[7:0] individual bits – LED: low value Red, high value Green
    • pause_vio_out – Active High Button
    • reset_vio_out – Active High Button
    • toggle_vio_out – Active High Button
    • vio_select – Toggle Button

    The resulting dashboard looks like this:



  6. Change the vio_select value to a 1. This disables the buttons on the physical board and enables the pause, reset and toggle buttons via the VIO.
  7. Select the pause button by clicking on the Value field of pause_vio_out. You will see the LED counter stop at a particular value. Take note of the unsigned binary value of the count_out_OBUF. In this screenshot, the value is 12.

  8. Press the toggle_vio_out button. The value of the count_out_OBUF bus be squared, as the current RM is a multiplier. In this case, 144.
  9. Press the pause button again and the counter will start. The count_out_OBUF values will now count by the square of 0 to 15. Ex. 1, 4, 9, 16, 25, etc.
    Note: Given the relative frequencies of the internal clock and the sampling rate of the Hardware Manager, you might not see all values in the sequence.
  10. Press the reset button to return the design to its default state. This count resumes to its initial 0 to 15 range.
  11. Play with these buttons to understand the design. If you have a local board, you can toggle the vio_select and use the buttons on the board and the LEDs on the board to observe the same behavior.
  12. Switch to the ILA dashboard. Up to this point you have used the VIO located in the static design. You can see the result of the multiplier, but if you want to observe the waveforms inside the RM, you can do this with the ILA located there.
  13. In the Trigger Setup window, press the + button and add the my_math/mult[7:0] probes. Change the radix (in both the Trigger Setup and waveform windows) to unsigned decimal and set the value to 196 (i.e. 14x14).

  14. In the settings window for the ILA, change the trigger position in the window to 512.

  15. Click on the run trigger button in the waveform toolbar. You will see the transition of the waveform from 169 to 196 (i.e. 132 to 142).
    Note: Make sure the VIO does not have the design paused, or the trigger will not occur.


  16. Now load the partial bitstream for the adder. Right-click on the target part in the Hardware view and choose Program Device.
  17. If you are targeting an UltraScale part, you must first program the clearing bitstream to prepare the design for the next partial bitstream. For the bitstream file choose the multiplier clearing bitstream. Navigate to the project_1.runs/impl1/ directory and choose the my_math_mult_partial_clear.bit file.

    The paired LTX file will be picked up automatically. Click Program.

  18. Switch to the VIO dashboard, and observe that the counter is still counting. If you press the toggle button to switch to the multiplier output, the value is held at 255. This is because the logic in the Reconfigurable Partition is currently disabled. Click the toggle button to switch back to the counter. Remember, vio_select must be set to a 1 to control remotely.
  19. Right-click on the target part in the Hardware view and choose Program Device.
  20. For the Bitstream file, navigate to project_1.runs/child_0_impl_1/ and choose the my_math_add_partial.bit file.

    Once again, the matching LTX file will populate automatically. Click Program.



  21. On the VIO dashboard, select pause. In this case, the value stopped at 6. After a toggle, the value is 18. The adder adds the same number 3 times.
  22. Switch to the ILA dashboard. In the Trigger Setup window click + and add my_math/outtemp2[5:0] bus. Change the following settings for the trigger:
    • Radix = [U] (unsigned decimal)
    • Value = 30
  23. In the ILA settings window change the trigger position to 512.
  24. In the waveform window, click the + button and add the my_math/outtemp2[5:0] bus to the waveform. Right-click on the probe and change the radix to unsigned decimal.
  25. In the waveform window, click the trigger button for the ILA. You will see the transition from 27 (9+9+9) to 30 (10+10+10).
    Note: Make sure the VIO does not have the design paused.


    Close the Hardware Manager when you are satisfied that everything is functioning properly.