Step 2: Loading Initial Design Sources - 2024.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

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2024.1 English

The first unique step in any DFX design flow (project based or otherwise) is to define the parts of the design to be marked as reconfigurable. This is done via context menus in the Hierarchical Source View in project mode.

  1. Extract the design from the TSC archive. The dfx_project_debug data directory is referred to in this tutorial as the <Extract_Dir>.
  2. Open the AMD Vivado™ IDE and select Create Project, then click Next.
  3. Select the <Extract_Dir> as the Project location. Leave the Project name as project_1, and leave the Create project subdirectory option checked. Click Next.
  4. Select RTL Project and ensure the Do not specify sources at this time check box is unchecked, then click Next.
  5. Click the Add Files button and select these sources to add to the design:
    • <Extract_Dir>\Sources\hdl\top.v
    • <Extract_Dir>\Sources\hdl\multiplier\mult.v
    • <Extract_Dir>\Sources\ip\<board>\clk_wiz\clk_wiz_0.xci
    • <Extract_Dir>\Sources\ip\<board>\vio\vio_0.xci

    Do not select add.v or mult_no_ila.v (in the adder and multiplier_without_ila folders, respectively), as these are the sources for RMs that will be added later.

  6. Select the Copy sources into project check box.
  7. Click Next to get to the Add Constraints page, then click the Add Files button, and select the following file: <Extract_Dir>\Sources\xdc\top_io_<board>.xdc
  8. Select the Copy constraints files into project checkbox.
    Note: These constraint files are full design constraints, scoped to the top-level design. This constraint file does not include a floorplan.
  9. Click Next to choose the part. In the Default Part page, click on Boards and (using filters if needed) choose the appropriate target platform:
    • AMD Kintex™ UltraScale™ KCU105 Evaluation Platform
    • AMD Virtex™ UltraScale™ VCU108 Evaluation Platform
    • AMD Kintex™ UltraScale+™ KCU116 Evaluation Platform
    • AMD Virtex™ UltraScale+™ VCU118 Evaluation Platform
  10. Click Next and then Finish to complete project creation. The Sources window shows a standard hierarchical view of the design.

    If red lock icons appear on either IP, as shown above, select Reports > Report IP Status to see if they can be upgraded. Ensure any out-of-date IP are checked, then click Upgrade Selected to bring them to the most recent version available. Leave Core Container disabled and click Skip when asked to generate output products.

    At this point, a standard project is open. Nothing specific to Dynamic Function eXchange has been done yet. Next, you will add an ILA core.

  11. In the Flow Navigator, under Project Manager, open the IP Catalog, and select Debug & Verification > Debug.
  12. Right-click ILA (Integrated Logic Analyzer), and select Customize IP. Customize the IP with these non-default options on the General Options and Probe_Ports(0..0) tabs:
    • Component Name: ila_mult
    • Input Pipe Stages: 1
    • Probe Width of PROBE0: 8

  13. Click OK and then Skip to create the IP.

    Do not select Generate. Leave the Synthesis Options set to Out of context per IP.

    This IP now fills in underneath the my_math hierarchy. The ILA core monitors the multiply function. You have now completed a full design hierarchy.