DFX Debug in a Versal Device - 2024.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Release Date
2024-06-12
Version
2024.1 English

The capabilities of debug within DFX designs in Versal devices continue from the flow supported in UltraScale+. Once instantiated, debug cores can be automatically connected to the HSDP in Versal device like was done for BSCAN, as long as the ports on the Reconfigurable Partition boundary has been defined. In UltraScale+ this was done with a set of 12 explicitly named S_BSCAN ports (or tagged with properties), whereas in Versal, connection to the HSDP is accomplished via the NoC.