Monitor Dynamic Function eXchange via Debug Cores - 2024.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Release Date
2024-06-12
Version
2024.1 English
Vivado debug cores have been inserted in this design, allowing you to monitor activity during Dynamic Function eXchange events. A key detail for configuring via the ICAP is to have prepared the partial bitstreams with the right bit and byte ordering for each .bin file.
  1. In the Vivado Hardware Manager, refresh the device to find all the Vivado Debug cores. There are three ILA cores, one VIO core and one MIG core in this design.
  2. Right-click the part in Hardware Menu, and select Hardware Device Properties. In the General tab, point the probes file to Bitstreams/top_count_up_shift_right.ltx.
  3. In hw_ila_2, click the + to add probes in the Trigger Setup window.
  4. Select SLOT_2_ICAP_i_1[31:0] and click OK. Change the Radix to [H] for hexidecimal.
  5. Set the trigger in the Trigger Settings window to a value of 5599_AA66, which is the configuration sync word, bit-swapped.
  6. Set the trigger position in the Settings window to 980.



  7. Select the Run Trigger button in the Hardware Manager GUI.
  8. On the board, push one of the pushbuttons other than the center to trigger reconfiguration of the shifter or counter. Or, perform this action via the UART terminal.
  9. In the resulting captured waveform, note a few things:
    • Far to the left, one of the rm_decouple signals (depending on which Reconfigurable Partition you have chosen to reconfigure) has transitioned from low to high. This isolation is initiated in the design prior to partial bitstream delivery
    • The sync word is preceded by 000000dd and then 88440022, which are the bit-swapped bus width detection
    • The ICAP output transitions from ffffff9b (no sync, no error) to ffffffdb (sync, no error). This transition shows recognition of the sync word, and the configuration engine is now expecting bitstream data.
    • PRDONE transitions high to low much further to the right, out of the range of this captured waveform.


    Note: Bitstreams will have multiple sync-desync pairs, as they are constructed via multiple segments. Multi-SLR devices, for example, have more due to bitstream formatting per SLR.
  10. Change the Value of the ICAP_i port to 0000_00B0, which is the desync word, bit-swapped.
  11. Set the trigger position in window to 512.
  12. Arm the trigger again and issue a reconfiguration.

    The resulting waveform shows the end of this part of the reconfiguration sequence, and shows PRDONE going high a few clock cycles after the desync word was seen.