Bottom-Up IP Integrator Design Creation Approach - 2024.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Release Date
2024-06-12
Version
2024.1 English
  1. Open AMD Vivado™ , and in the Tcl Console navigate to the folder where the design scripts and constraint file are located.
  2. Source this script to generate the block designs for this lab.
    source create_ipi.tcl

    The create_ipi.tcl script calls four underlying scripts, each of which creates an individual block design. The first three are reconfigurable modules (RM), and the fourth is a top block design that uses a block design container to reference the individual reconfigurable modules. Given that the RMs are created before the top-level, this is considered a bottom-up approach.

    Once the design creation is complete, you will observe the design is divided into one static region and one reconfigurable partition.



    The static_region is a level of hierarchy that sets up the management of the design. It includes CIPS, NoC (with DDR), clocking, and reset. It also includes a static debug hub, an ILA core, and a DFX decoupler instance.



    Reconfigurable Module rp1rm1 is the default RM and can be seen when expanding the Block Design Container rp1. This first module has an up counter connected to ILA. This ILA will be stitched to the Debug Hub in the rp1rm1 during opt_design of the parent run.



    Reconfigurable Module rp1rm2 has a down counter connected to VIO. This debug core will also be stitched to the Debug Hub in rp1rm2 during opt_design of the first child run.



    Reconfigurable Module rp1rm3 has a down counter and up counter connected to two AXI GPIOs. Both counters are connected to separate ILAs. Both of the ILAs, along with a VIO core, will be connected to the Debug Hub in rp1rm3 during opt_design of the second child run.



    Note: This tutorial shows the ChipScope instantiation flow, where ILA and VIO cores are explicitly added to the design on the block design canvas. The Vivado tools also supports the ChipScope insertion flow, where signals are tagged for debug and core details are added after synthesis. For an example of the insertion flow, see the DFX Debug Tutorial available from the GitHub repository.
  3. Enable HSDP1 for CIPS.

    Follow the steps from the HSDP tutorial to enable HSDP for high speed debug. Confirm that the Aurora-based HSDP has been enabled by opening the CIPS IP > PS PMC > Debug selection > HSDP tab.



    To complete the set of design sources, first add the constraint file that defines the Pblock for the reconfigurable region. Alternatively, you can create this Pblock yourself after synthesis.

  4. Use the Add Sources button to add the Pblocks constraint file, or call this command on the Tcl Console:
    add_files -fileset constrs_1 -norecurse ./pblocks.xdc

    Next, create the HDL wrapper for the top-level block design.

  5. Right-click design_1.bd and select Create HDL Wrapper > OK to have this file auto-generated and added to the project. The corresponding Tcl for this action is:
    make_wrapper -files [get_files ./dfx_debug_abs/dfx_debug_abs.srcs/sources_1/bd/design_1/design_1.bd] -top