Step 3: Completing the Design with the Dynamic Function eXchange Wizard - 2024.1 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)

Document ID
UG947
Release Date
2024-06-12
Version
2024.1 English
  1. Launch the Dynamic Function eXchange Wizard by selecting this option under the Tools menu or from the Flow Navigator.
  2. Click Next to get to the Edit Reconfigurable Modules page. Here you can see the shift_right RM already exists, and there are add, remove and edit buttons on the left hand side of the window, above the RMs. Click on the blue + icon to add a new RM.
  3. Click the Add Directories button to select the shift_left folder:
    <Extract_Dir>\Sources\hdl\shift_left

    Or use the Add Files button to select the shift_left.v file residing in this directory. If module-level constraints were needed, they would be added here and would need to be scoped to the level of hierarchy for this Partition.

    Fill in the Reconfigurable Module field to be shift_left. Set the Partition Definition to be shifter, leave Top Module field empty and the Sources are already synthesized check box unchecked. Click OK to create the new module.

    Two Reconfigurable Modules are now available for the shifter Reconfigurable Partition. Click Next to continue.



    On the next page, Configurations are defined. Configurations are full design images consisting of the static design and one RM per RP. You can either create any desired set of configurations, or simply let the wizard select them for you.

  4. Select the automatically create configurations link to let the Wizard create the configurations.

    After selecting this option, the minimum set of two configurations is created. Each shift instance is given shift_right in the first configuration and shift_left in the second configuration.

    Note: The Configuration Name is editable. In the example below, the names are updated to config_right and config_left to reflect the Reconfigurable Modules contained within each one.


    Additional configurations can be created by using these two Reconfigurable Modules, but two is all you need to create all the partial bitstreams necessary for this version of the design, as the maximum number of RMs for any RP is two (not including greybox RMs).

  5. Click Next to get to the Edit Configuration Runs page.

    As with configurations themselves, the runs used to implement each configuration can be automatically or manually created. A parent-child relationship will define how the runs interact – the parent run implements the static design and all RMs within that configuration, then child runs reuse the locked static design while implementing the RMs within that configuration in that established context.

  6. If targeting UltraScale+ devices, click the Standard DFX link to populate the Configuration Runs page with the minimum set of runs. Abstract Shell configuration runs are covered in a different lab.

    If targeting 7 series or UltraScale devices, click automatically create configuration runs to populate the Configuration Runs page with the minimum set of runs. The Abstract Shell flow is not available for these architectures.

    Note: The following figures show a design that targets an UltraScale+ device.


    This creates two runs, consisting of one parent configuration (config_right) and one child configuration (config_left). Any number of independent or related runs can be created within this wizard, with options for using different strategies or constraint sets for any of them. For now, leave this set to the two runs set here. The names of the runs are not editable.



  7. Click Next to see the Summary page, and click Finish to complete the design setup and exit the Wizard.
    Important: Nothing is created or modified until you click Finish to exit the DFX Wizard. All actions are queued until this last click, so it is possible to step forward and back as needed without implementing changes until you are ready.

    Back in the AMD Vivado™ IDE, you will see that the Design Runs window has been updated. A second out-of-context synthesis run has been added for the shift_left RM, and a child implementation run (child_0_impl_1) has been created under the parent (impl_1). You are now ready to process the design.