PCI Express® is a plug-and-play protocol, that is, at power up the PCIe host enumerates the system, including assigning base addresses to the PCIe devices. Therefore, the PCIe interfaces must be ready when the host queries the interfaces, or the interfaces are not assigned a base address. The PCI Express specification states that PERST# can deassert 100 ms after the power good of the systems has occurred, and a PCI Express port must be ready to link train 20 ms after PERST# has deasserted. This is commonly referred to as the 100 ms boot time requirement, even though 120 ms is the goal.
Versal devices can meet this 120 ms link training requirement by using Tandem Configuration, a solution that splits the programming image into two stages. The first stage quickly configures the PCIe Endpoints so that the Endpoint is ready for link training within 120 ms. The second stage then configures the rest of the device. Two variants are supported:
- Tandem PROM
- Loads both stages from a single programming image from a standard primary boot interface.
- Tandem PCIe
- Loads the first stage from a primary boot interface. Then, the second stage is delivered via one of the CPM PCIe controllers.
Within the Versal adaptive SoC, the CPM consists of two PCIe controllers, DMA features, CCIX features, and network on chip (NoC) integration. The Versal Adaptive SoC CPM Mode for PCI Express enables direct access to the two high-performance, independently customizable PCIe controllers. You can specify whether to have one or both of these controllers enumerate within 120 ms using Tandem Configuration. Not every device has a CPM, so if 120 ms enumeration is a requirement for your system, be sure to select a device that can meet this goal.
Tandem Configuration and Dynamic Function eXchange (DFX) are solutions for different phases of device operation. Tandem Configuration is only used at the initial power-up of the device or after a full device reconfiguration request to bring up the device in stages. DFX is used during normal operation to deliver programming images that modify a portion of the programmable logic while the rest of the device remains active.
For the following monolithic devices, you can select both Tandem Configuration and DFX in a single design, allowing you to benefit from the advantages of both solutions:
- All Versal AI Core devices with CPM4 or CPM5
- All Versal AI Edge devices with CPM4 or CPM5
- All Versal Prime devices with CPM4 or CPM5
- Monolithic Versal Premium devices with CPM4 or CPM5 (VP1002, VP1052, VP1202)
The CPM is a resource customized within the CIPS IP and must reside in the static domain of a DFX design. You must take care to keep any DFX Pblocks away from the PS-PL boundary where soft logic associated with the CPM is placed. Failure to do so might result in an unrouteable design.
When using DFX in Versal devices with CPM resources, you can use the DMA functionality to deliver partial PDI images from a PCIe host to the PMC for partial reconfiguration. You can manage DMA transfers (QDMA for CPM4 or CPM5, XDMA for CPM4 only) using drivers provided by AMD. The aperture size must be set so the DMA transfer acts on a keyhole. A configurable example design (CED) is available within the AMD Vivado™ tools, showing the details of the Tandem PCIe solution, including the use of the QDMA driver to deliver the stage 2 programming image. You can use the same approach and driver to deliver partial images for DFX during normal operation of the design.
For more information on PCIe functionality, Tandem Configuration, and PDI delivery via CPM DMA, see the Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).