Dynamic Function eXchange through ICAP for Zynq Devices - 2024.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-06-12
Version
2024.1 English

The primary configuration mechanism for the programmable logic (PL) of Zynq 7000 and Zynq UltraScale+ MPSoC devices is through the processing system (PS), which delivers bitstreams to the PCAP. The most common mechanism for partial reconfiguration is also through this path. However, to manage partial reconfiguration completely within the PL (either through the PR Controller IP or through a custom-designed controller module), partial bitstreams can also be delivered to the ICAP, just as they can be for FPGA devices.

The PCAP and ICAP interfaces are mutually exclusive and cannot be used simultaneously. Switching between ICAP and PCAP is possible, but you must ensure that no commands or data are being transmitted or received before changing interfaces. Failure to do this could lead to unexpected behavior.

To enable the ICAP for Zynq 7000 devices, set bit 27 (PCAP_PR) of the Control Register (devc.CTRL). This bit selects between ICAP and PCAP for PL reconfiguration. The default is PCAP (1), but that can be changed to ICAP (0) to enable this configuration port. Note that bit 28 (PCAP_MODE) must also be set to 1, which is the default. For more details, see the .

To enable the ICAP for Zynq UltraScale+ MPSoC devices, set the PCAP_PR field of the pcap_ctrl (CSU) register. This bit selects between ICAP (or MCAP) and PCAP for PL reconfiguration. The default is PCAP (1), but that can be changed to ICAP / MCAP (0) to enable this configuration port. For more details, see the Zynq UltraScale+ Device Technical Reference Manual (UG1085) and the Zynq UltraScale+ Device Register Reference (UG1087).

The Zynq UltraScale+ MPSoC Xilfpga library supports the delivery of partial bit files for Linux and bare-metal applications. In the current release, only non-secure bitstreams (without encryption or authentication) are supported. For more information and examples, visit the Xilfpga Wiki page (www.wiki.xilinx.com/xilfpga).