Static Routing Across SLR Boundaries - 2024.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-05-30
Version
2024.1 English

In SSI technology Versal devices, the SLL nodes crossing SLRs exit through CLE tiles. The routing of static nets or the static portion of boundary nets (that is, the part of the net between the PPLOC and static region) cannot use the slice route-through after crossing the SLR boundary within a reconfigurable partition (RP). If RP Pblocks span or are next to an SLR boundary, only routes within the reconfigurable modules (RMs) within that RP can cross that area. If non-NoC routes must traverse the SLR boundary, leave space on one or both sides of the RP Pblock to give space for route_design to find a solution.

The following figure shows a two-SLR VP1502 device with two RPs. The RP0 and RP1 Pblocks align with the SLR boundary (shown in red), and adequate space is provided on either side (shown in green) to ensure that static routes and static portion of boundary nets can cross the SLR boundary without any issues. Even though the DFX expanded routing feature expands left and right of the RP to obtain more resources, expanded routing does not use the SLLs in the expanded region, leaving those resources for the static design. The routing for the SLR0<--SLR1 static net is highlighted in red, because it requires the CLE inside RP0 to exit the SLL node, which is not allowed. The SLR0-->SLR1 static net is highlighted in green, because CLE resources from the static region are available in SLR1 to exit the SLL node.

Figure 1. Two-SLR VP1502 Device with Two Reconfigurable Partitions

When there are insufficient SLL nodes available to cross the SLR boundary, route_design fails with an SLL assignment error. The SLL assignment phase in route_design provides an SLL Capacity Report, which can be used debug to the error. The report is divided into the following tables:

SLL Capacity Report (DFX)
The information captured in this table is based on the DFX floorplan and shows the number of available SLLs per SLR pair for static routing and for each RP routing.
Net Demand Report (DFX)
The information captured in this table is calculated based on the DFX design placement and it shows static nets and RP nets, including both internal and boundary nets that require SLL nodes.

For each SLR boundary, the crossing capacity and the number of nets crossing are detailed per direction (North and South) and combined for both directions.

Tip: You can use the following Tcl command on a placed design to get all the SLR crossing nets in the design: get_nets -hierarchical -top_net_of_hierarchical_group -filter { CROSSING_SLRS =~ "*SLR*" }

The following figure shows an example floorplan for two RPs that cover the complete SLR boundary and highlighted boundary net from pblock_rp2rm1 (blue region), which requires an SLR crossing from SLR1-->SLR0.

Figure 2. Example Floorplan of Two Reconfigurable Partitions

In this example, the design fails during route_design and reports the following in the log file.

Figure 3. Log File for Example Floorplan of Two Reconfigurable Partitions

In the SLL capacity Report (DFX), the highlighted section indicates that the number of SLL nodes available for static nets is zero. Based on the DFX floorplan, routing through the CLE, which is part of RP, is not possible. Similarly, pblock_rp1rm1 (yellow region) has zero SLL nodes to route from 0->1 (SLR0 to SLR1), and pblock_rp2rm (blue region) has zero SLL nodes to route from 0<-1 (SLR1 to SLR0).

In the Net Demand Report (DFX), pblock_rp2rm1 (blue region) requires one boundary net to route from 0<-1 (SLR1 to SLR0). This is prohibited because the net crossing the SLR boundary needs to route through the CLE in pblock_rp1rm1 (yellow region).

The only way to cross pblock_rp1rm1 is to leave space at the device edges to allow the boundary nets to route through the CLE. This is a design-dependent decision.

Following is an example of a routed design with space left for static nets and boundary nets to cross the SLR.

Figure 4. Routed Design with Static Nets and Boundary Nets Crossing the SLR