Logical Decoupling - 2024.1 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2024-06-12
Version
2024.1 English

Because the reconfigurable logic is modified while the device is operating, the static logic connected to outputs of RM ignores the data from RM during partial reconfiguration. The RMs do not provide valid output data until partial reconfiguration is complete and the reconfigured logic is reset. It is not possible to predict or simulate the functionality of the RM. Logical decoupling isolates the dynamic part of the design from the static, ensuring no unintended activity disrupts the static design.

There are number of boundary types where logical decoupling should be inserted, based on the connectivity of the RP, and there are different strategies for each scenario. Boundaries can be within the PL, within the NoC, or at the PS-PL boundary.

Logical Decoupling at the PL Boundary

A common design practice to mitigate this issue is to register all output signals on the static side of the interface from the RP. An enable signal is used to isolate the logic until it is completely reconfigured. Other approaches include a simple 2-to-1 MUX on each output port or to higher level bus controller functions.

Two pieces of IP are available from AMD to provide decoupling capabilities in the PL. The DFX Decoupler IP allows user to insert multiplexers to easily and efficiently decouple AXI4-Lite, AXI4-Stream, and custom interfaces. This IP disables key signals to prevent unwanted activity on the RP boundary. The DFX AXI Shutdown Manager IP provides a more intelligent way to decouple AXI interfaces, offering different responses to requests rather than holding boundaries constant. More information about the DFX Decoupler IP is available on the Xilinx.com website.

Logical Decoupling in the NoC

If the boundary falls within the NoC, NoC quiescing is automatic only if the NMU/NSU is inside the RP. If the NoC/PL AXI interface is at the RP boundary, a logical decoupler is still required. In such a case, it is recommended to put the interface NoC in the RP to avoid the use of the AXI decoupler. Then the connection across partitions is no longer AXI-based but based on the NoC internal path through INI.

Although NoC quiescing occurs automatically and allows you to bypass IP that uses PL, such as the DFX AXI Shutdown Manager or DFX Decoupler, you must oversee AXI transactions to and from the RP during reconfiguration. Outstanding AXI transactions across DFX partitions during reconfiguration can lead to NoC timeout errors at NMU or NSU in the static domain. Additionally, prolonged delays on ready signals are identified by NMU/NSU, potentially causing AXI handshake timeouts. You can examine the NMU/NSU interrupt status register (ISR) to assess if the interrupt register based on timeouts is high.

Logical Decoupling at the PS-PL interface

If the boundary between static (PS) and dynamic (PL) is specifically at the PS-PL interface, the following use cases apply:

  • If the entire PL is included in the dynamic region, partial reconfiguration includes a power domain shutdown such that the entire PL is temporarily powered down.
  • The static design should include the functional behavior required for the data and interface management. It can implement mechanisms such as handshaking or disabling interfaces, which might be required for bus structures to avoid invalid transactions. It is also useful to consider the down-time performance effect of a dynamic module, that is, the unavailability of any shared resources included in the dynamic module during or after reconfiguration. This is the most common scenario.